About |
Recent years have witnessed the emergence of computing architectures that integrate up to a thousand processor cores and memory on a single die as a result of relentless semiconductor device scaling. This opens up a plethora of architectural challenges in terms of efficiency or specialization, among others, and supports the spread of various applications and novel computational paradigms, ranging from massive manycore processing to reconfigurable, quantum, in-memory, or neuromorphic computing. As a side effect of such wild increase in integration, communication (and not computation) has gradually become the main determinant of performance in nowadays computers. To address this, processors integrate interconnection networks that manage the movement of data in a scalable and cost-effective manner at the chip scale, i.e., for ranges between hundreds of nanometers to a few millimeters. The main challenge is for these chip-scale nanonetworks to provide the efficiency, versatility, scalability and reliability necessary to tackle the growing technological, architectural and workload heterogeneity in this new era of computing. The special issue seeks contributions addressing the different challenges of chip-scale nanocommunications and networking, putting emphasis on emerging technologies (e.g., wireless, RF interconnects, optics), new approaches (e.g., approximate computing, machine-learning-based design) and disruptive applications (e.g., quantum computers). The editors equally welcome submissions about physical prototypes realizable in the near future and more prospective contributions with clear longer-term potential. While the scope of the special issue revolves around communications and networking aspects, submissions discussing frontier aspects such as memory architectures, 2.5D/3D packages, or application mapping are also welcome. |
Call for Papers |
Topics of InterestThe special issue solicits high-quality and original contributions on topics including, but not limited to:
Submission InstructionsProspective authors shall submit their papers through the submission portal, choosing the option "VSI: Chip-Scale Nanonetworks" in the issue selection stage. The submitted manuscripts should not have been previously published nor should be currently under consideration for publication elsewhere. Important DatesThis special issue follows a continuous and expedited review process. Papers will be start being reviewed shortly after they are submitted. The review-to-acceptance process is aimed at being no longer than 4 months. Manuscript submissions due: 28 February 2020 Notification of acceptance: 15 June 2020 Final manuscripts due: 1 July 2020 |
Credits and Sources |
[1] NANOCOMNET-SI 2020 : Special Issue on Chip-scale Nanonetworks: Recent Trends, Emerging Technologies, Disruptive Applications |